The present disclosure generally relates to memory systems, and more specifically, to a memory module with a distributed, serialized data buffer for a cascadable, extended memory system.
Modern computer memory systems typically store data or information within memory modules, examples of which include single-in-line memory modules (SIMMs), dual-in-line memory modules (DIMMs), and the like. Each memory module includes a plurality of discrete memory devices, such as dynamic random access memory (DRAM) devices, asynchronous DRAM devices, synchronous DRAM (SDRAM) devices, etc., that can be accessed, via one or more buses, by a processor or memory controller. The plurality of memory devices are typically organized into ranks, which generally refers to a set of memory devices that can be selected (or accessed) via the same control signal from the processor or memory controller.
In addition, most memory systems today employ double data rate (DDR) memory, which is a type of SDRAM. DDR memory, in general, provides increased access speed by transferring data on both the rising and falling edges of a clock signal. Examples of DDR SDRAM include any of the versions of the DDR SDRAM specification from JEDEC (e.g., DDR4 SDRAM, DDR3 SDRAM, DDR2 SDRAM, etc.). DDR memory, now in its fourth generation (e.g., DDR4 SDRAM), is characterized by bidirectional data lines, with one signal contact per line (generally referred to as single-ended signaling). In addition, there is a unidirectional, single-ended command and address bus, which generally runs at half the speed of the data bus. The DRAM clock uses two signal contacts per line, each an inverse of the other (generally referred to as differential signaling).
As the demand for faster memory continues to increase, modern electronic devices such as processors and memory continue to improve by operating the devices at higher clock speeds. However, as computers and computer processors continue to increase in performance, the need to operate at higher clock speeds has prompted new issues to emerge as areas of concern. One such issue relates to increased latency experienced when accessing DRAM devices within a memory module.